This invention relates, in general, to low power integrated circuit designs, and more particularly, to reducing power consumption of an integrated circuit.
The power consumption of an integrated circuit is always a critical performance parameter. The increase in circuit density due to smaller device geometries and the prevalent use of battery power has raised the importance of reducing power consumption to a high level. Complementary Metal Oxide Semiconductors (CMOS) has been a popular technology for low power circuits. CMOS is considered a low power integrated circuit process due to the low power dissipated under static conditions. A CMOS gate in a static condition does not have a DC bias current to dissipate power. Power dissipation from a CMOS circuit is due to reverse biased junction leakage currents which are normally extremely small in magnitude.
Other technologies such as Emitter Coupled Logic (ECL) or Current Mode Logic (CML) dissipate power under static conditions. The technologies that dissipate power under static conditions typically use current sources to bias circuitry. Although static power is dissipated in circuitry using current sources they are well known for providing high performance. The static power dissipation of these types of circuits prevent there use in many low power applications.
It would be of great benefit if a circuit and method could be developed that reduces power dissipation in circuits having current sources thereby allowing their incorporation in low power circuits to enhance performance.